Scaling of metal oxide semiconductor (MOS) devices is provided through many techniques. For example, a current technique is the use of metal replacement gates using a damascene scheme. In this approach, a dummy gate is formed on a semiconductor wafer through using standard polysilicon gate CMOS process flow. For example, a dielectric layer and polysilicon layer are deposited on the semiconductor substrate, which are then patterned to form the dummy gate. Source/drain regions can be formed on the semiconductor using conventional implantation processes. An insulator layer can then be deposited about the dummy gate. The insulator layer is then polished to expose the polysilicon layer of dummy gate. The dummy gate is then removed by reactive ion etching (RIE) and/or wet chemical etching to form to form a trench in the insulator layer.
To form the replacement metal gate, metal is then deposited within the trench. However, during the metal fill, metal begins to pinch-off the opening of the trench, prior to the trench being filled. When this occurs, a void or cavity is formed in the trench (due to the difficulty of filling capability). Accordingly, the void or cavity formation due to the pinch-off phenomenon, in turn, limit the scalability of this scheme for the future technology nodes.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.